1. Field of the Invention
Disclosed herein are a semiconductor device and a fabrication method thereof.
2. Description of the Related Art
Efforts for developing technologies for Si-based semiconductors have been focused on reducing the linewidth of devices for recent 10 years. Semiconductor companies such as Samsung, Hynix and Intel have made efforts to reduce the linewidth of devices from 30 nm to 20 nm and then to 15 nm. However, it is considered that if the line width of the device finally reaches 10 nm, it is impossible to develop technologies for reducing the Si linewidth. Currently, a group III-V complementary compound semiconductor device, a carbon nanotube, a nanoline technology are proposed as technologies to be substituted for the technologies for Si-based semiconductors posterior to Si semiconductors. [R. F. Service, “Is Silicon's Reign Nearing Its Ends?”, Science, vol. 323, pp. 1000-1002, Feb. 20, 2009] Among these technologies, it is expected that the group III-V complementary compound semiconductor devices will be realized fastest. Although compound semiconductors have electron mobility 10 to 100 times greater than Si semiconductors, it is difficult to implement digital logic devices using the compound semiconductors. This is because there are various technical problems. Among these problems, it is the most serious problem to implement p-type group III-V semiconductors device using holes as carriers.
This is because a complementary structure in which an n-type semiconductor device using electrons as carriers and a p-type semiconductor device using holes as carriers are combined together is necessarily required in logic devices. That is, the complementary structure hardly requires electric power for memorizing the state of logic, but the structure using only electrons or holes as carriers requires electric power for maintaining a record. However, although representative group III-V semiconductors such as GaAs and InP have fast electron mobility, their hole mobility is hardly different from that of Si semiconductors (see FIG. 1). Further, in spite of the fast electron mobility, the operating speed of complementary semiconductor devices using the group III-V semiconductors are hardly faster than that of the Si semiconductors. Hence, it is unnecessary to fabricate semiconductor devices using a high-priced group III-V semiconductor substrate. Therefore, in practical applications, compound semiconductor devices that operate at a high speed of more than 500 GHz consume more powers than complementary Si semiconductor devices. Accordingly, the compound semiconductor devices are frequently used as analog devices such as high-speed amplifiers rather than logic devices. In a case where the compound semiconductor devices are used as the logic devices, they are partially applied to military logic devices.
However, since year 2000, group III-V semiconductor devices that operate 2 to 3 times faster than p-type Si semiconductor devices have been fabricated using a method for increasing hole mobility by modifying the band gap structure of light and heavy holes using a strain. In 2008, it was reported that p-type group III-V semiconductor devices fabricated through a 0.2 μm pattern process were operated at 34 GHz. With the continuous development of semiconductor devices, it is expected that group III-V based complementary logic devices will be developed in five years. [J. B. Boos et al., “Sb-based n- and p-channel heterostructure FETs for high-speed, low-power applications”, IEICE Transactions on Electronics, vol. E91c, pp. 1050-1057, Jul. 2008]
FIG. 1 is a table showing electron and hole mobilities of various semiconductor materials, measured at normal temperature. In existing inventions and studies, two-dimensional hole gas (2DHG) with a type-1 quantum well structure is generated by applying the fast hole mobility of Ge [G Hook et al., “Carrier mobilities in modulation doped Si1-xGex heterostructures with respect to FET applications”, Thin Solid Films, vol. 336, pp. 141-144, Dec. 30, 1998] or by using InSb or GeSb, and hole mobility is increased by adding a strain effect to the 2DHG. [J. B. Boos et al.]
SiGe semiconductor device is fabricated as a complementary semiconductor device by combining a small amount of Ge with existing Si, so that an existing Si process can be used in the fabrication of the SiGe semiconductor device. Because of the lattice mismatch between Si (0.54 nm) and Ge (0.57 nm), there exists another technical problem in injecting a large amount of Ge into Si. Therefore, the electron and hole mobilities of Si containing a small amount of Ge are higher than those of pure Si but lower than those of another group III-V semiconductor and pure Ge. Hence, the fabrication of SiGe semiconductor device is considered as an intermediate technology between Si technology and group III-V semiconductor technology.
Since InSb or GaSb has high hole mobility (see FIG. 1), it is suitable for 2DHG of p-type semiconductor devices, but the quantum wall of a semiconductor such as AlGaSb with a lattice coefficient of more than 0.6 nm is required to grow InSb or GaSb using the type-1 quantum well structure. In addition, the InSb or GaSb is not lattice-matched with GaAs (0.56 nm) or InP (0.58 nm) that can be easily obtained. Therefore, a new growth technology such as meta-morphic is required, and new processes such as etching and metal bonding are necessarily designed.